Static random access memory (SRAM) devices are employed extensively in many semiconductor devices for their non-volatile characteristics. An SRAM includes six transistors. As illustrated in FIG. 1, two pairs of series connections of a pull-up PFET (M2 or M4) and a pull-down NFET (M1 or M3) are provided between a power supply voltage VDD and electrical ground. The gate electrodes of each series connection are electrically shorted to each other, and are electrically shorted to a node between the pull-up PFET (M2 or M4) and the pull-down NFET (M1 or M3) to provide cross-coupling between two complementary nodes (Q and Q_bar) of the two pairs of series connections. Two pass gate transistors (M5 and M6) are controlled by gate electrodes connected to a common word line WL, and are connected two complementary bit lines (BL and BL_bar) that provide opposite signals. The states of the two complementary nodes (Q and Q_bar) are self-stabilizing and self-perpetuating, thereby enabling preservation of preservation of the states of the two complementary nodes (Q and Q_bar) when external power is turned off.
In conventional SRAMs known in the art, pull-up PFETs employ a p-doped semiconductor material for gate electrodes, and pull-down NFETs and pass gate transistors employ an n-doped semiconductor material to provide optimal gate work functions. The p-doped semiconductor material of the gate electrodes of the pull-up PFETs and the n-doped semiconductor material of the gate electrodes of the pull-down NFETs cannot be connected directly due to formation of p-n junctions therebetween. To avoid formation of p-n junctions, a pair of contact via structures and at least one metal interconnect line structure are employed to provide the electrical connection between the gate electrodes of the pull-up PFETs and the pull-down NFETS.